1. Field of the Invention
The present invention relates to circuitry to aid in the routing of electrical signals from one location to another, such as from one semiconductor-based device to another. In particular, the present invention relates to the selection of particular electrical signals for transfer. More particularly, the present invention relates to multiplexers for selection/de-selection of electrical signals to be routed, including, but not limited to, emitter-coupled logic (ECL) signals.
2. Description of the Prior Art
Circuits designed to aid in the selection of one or more electrical signals for routing from one device to another are commonly referred to as multiplexer circuits. Multiplexing circuits generally include a plurality of gating mechanisms that permit one and only one signal from a plurality of incoming signals to pass through from one device to another. Those devices may be on the same chip (as in the case of a microprocessor) or on different chips (such as between a memory device and a microprocessor). In the case of ECL multiplexers in particular, the selected signal is actually a complementary pair of signals selected from a plurality of complementary input signal pairs.
The continuing interest in achieving faster processing rates in most electronic systems affects all components thereof, including ECL-based multiplexers. It is well known that bipolar-transistor-based ECL is one of the fastest logic families available. The difference in the potentials associated with an ECL high signal and an ECL low signal is generally on the order of 0.4V to 1.6V. That is, the peak-to-peak voltage differential (Vpp) between a logic high and a logic low may be as small as 0.4V.
One example of a high-speed ECL multiplexer operating generally under those potential swings is illustrated in FIG. 1. The prior-art multiplexer illustrated in that drawing includes an exemplar plurality of inputs including a first set of complementary inputs, input and input.sub.-- bar and a second set of complementary inputs, input2 and input2.sub.-- bar. A selection input select provides the control signal for defining which of the input pairs is to be selected by the multiplexer for delivery of a single complementary output signal pair designated by output and output.sub.-- bar. The pathway for the first set of complementary inputs includes a first differential amplifier DA1, a first pass gate driver set PGD1, a first pass gate PG1, an output differential amplifier ODA, and output drivers Q52 and Q51 to buffer and shift the levels of outputs output and output.sub.-- bar, respectively. The pathway for the second set of complementary inputs is similarly configured.
The first differential amplifier DA1 and the second differential amplifier DA2 each includes a pair of bipolar transistors, Q68, Q69 and Q76, Q77. Those differential transistors have their collector nodes coupled to the high-potential power rail Vcc, either directly, or through potential-setting resistances, shown in FIG. 1 as resistances R66, R67 and R70, R71. These resistances set the potential at the control nodes of the pass gate driver sets PGD1 and PGD2. The extra set of drivers provided by transistors Q51 and Q52 are required to increase the signals provided by the pass gate transistors as those MOS transistors must be relatively small in order to be fast, as is well known to those skilled in the art.
It can be seen in the operation of the multiplexer shown in FIG. 1 that the pass gate transistors charge up the control nodes of the transistors of the output differential amplifier ODA. That amplifier in turn regulates the operation of the output drivers Q51 and Q52. The required charging up of the capacitance associated with the transistors of that stage of the circuit could lead to undesirable transient signal noise.
The ECL multiplexer illustrated in FIG. 1 is less efficient in operation than is desirable and possible. That is, the delay associated with the signal transfer through the pass gates and the powering up of the transistor used to configure the output differential amplifier alone is on the order of 500 picoseconds. In order to advance the state of microprocessing, it would be advantageous to minimize delays without sacrificing performance.
Therefore, what is needed is a multiplexer that may be incorporated into any logic operation system and that provides faster switching times than presently available. What is also needed is such a multiplexer that is substantially limitless in regard to the number of inputs to be multiplexed, and that provides for satisfactory signal transfer with, to the extent possible, minimal switching noise.